📚 Assignment 6 CMPE1250: Clock Library

📋 Overview

By completing this assignment, students will be able to:

Interpret the STM32G0 clock tree and PLL architecture
Configure the PLL safely (disable → configure → enable → switch SYSCLK)
Update SystemCoreClock correctly
Output the system clock on MCO (i.e. PA8 or PA9)
Cycle through multiple PLL configurations using a button (i.e. PC13)
Validate clock changes using an oscilloscope
Implement simple state‑based input handling (button press detection)

This mirrors real embedded engineering workflows and reinforces practical debugging skills.

1️⃣ Safe PLL Reconfiguration Sequence

Ensure HSI16 is enabled
Switch SYSCLK away from PLL
Disable PLL
Wait for PLLRDY to CLEAR
Write PLL configuration (source, M, N, R)
Enable PLL
Wait for PLLRDY to SET
Switch SYSCLK to PLL
Update SystemCoreClock

Question: Why must the system clock be switched away from PLL before disabling it?

2️⃣ Implementation

Fill out the remaining PLL configurations in the PllRange enum in clock.h (i.e. 20MHz, 24MHz, 32MHz, 40MHz, 48MHz, 50MHz, 60MHz, and 64MHz). You will need to calculate the appropriate values for M, N, and R for each configuration.

typedef enum PllRangeTypedef__
{                //              R                       N                          M   
    PLL_16MHZ = (8-1)<<RCC_PLLCFGR_PLLR_Pos |  8<<RCC_PLLCFGR_PLLN_Pos | (1-1)<<RCC_PLLCFGR_PLLM_Pos,
    PLL_20MHZ,,
    PLL_24MHZ,
    PLL_32MHZ,
    PLL_40MHZ,
    PLL_48MHZ,
    PLL_50MHZ,
    PLL_60MHz,
    PLL_64MHZ, 
}PllRange;  

- Document the M, N and R for each PLL configuration in the markdown file, along with the expected output frequency.

- Code the 2 functions provided in the header file `clock.h` to implement the PLL reconfiguration sequence and MCO output.

  void Clock_InitPll(PllRange);
  void Clock_EnableOutput(MCO_Select, MCO_Div);

3️⃣ Clock Settings verification

Create a program that does the following:

Use the SystemCoreClock variable to verify that the system clock frequency is updated correctly after each PLL configuration change.
Display the current system clock frequency in [MHz] at startup and after each change on the debug terminal.
Enable the MCO output, using a prescaler of 8, and use an oscilloscope to verify that the output frequency on MCO (i.e. PA8 or PA9) matches the expected frequency for each PLL configuration.
Create a feature that cycles through the PLL configurations each time a button is pressed (i.e. PC13), and outputs the system clock on MCO (i.e. PA8 or PA9).
After each button press, use the oscilloscope to verify that the output frequency on MCO matches the expected frequency for the new PLL configuration (divided by 8).
When cycling through the last PLL configurations, wrap around back to the first PLL configuration.