Interrupts Continuation

📚 Lesson: Interrupt Priority and Advanced NVIC Functions

1️⃣ How Interrupt Priority Actually Works (Cortex‑M0+)

The Cortex‑M0+ has three classes of interrupt-like events:

  1. Reset (highest priority)
  2. Core exceptions
    • HardFault
    • SysTick
  3. Peripheral interrupts (TIM6, USART, ADC, EXTI, etc.)

The key idea:
👉 Core exceptions always outrank peripheral interrupts.

Within peripheral interrupts, priority is determined by the IRQ number (lower number = higher priority).

2️⃣ Example: SysTick vs TIM6 — Who Wins?

Let’s compare them:

Interrupt Source Type Priority Level Notes
SysTick Core exception Higher than any peripheral Fixed priority, cannot be lowered
TIM6_DAC_LPTIM1_IRQn Peripheral IRQ Lower than SysTick Priority based on IRQ number

So if SysTick and TIM6 fire at the exact same moment:

✔ SysTick ISR runs first

✔ TIM6 ISR waits in the pending state

✔ When SysTick ISR finishes, NVIC immediately dispatches TIM6 ISR

This is a great example of preemption and pending state behavior.

3️⃣ Timeline Example

Imagine both events occur on the same CPU cycle:

t0: TIM6 update event occurs → TIM6 interrupt flag set
t0: SysTick counter hits 0 → SysTick event generated
t0: NVIC checks priorities
t0: SysTick wins → CPU enters SysTick_Handler

t1: SysTick_Handler runs
t2: SysTick_Handler returns

t3: NVIC sees TIM6 still pending → CPU enters TIM6_DAC_LPTIM1_IRQHandler
t4: TIM6 ISR runs
t5: TIM6 ISR returns

This is a great demonstration of:

  • Priority resolution
  • Pending state
  • Tail‑chaining (if another interrupt is waiting, the CPU jumps directly to it without restoring main context)

4️⃣ Why SysTick Always Wins

SysTick is part of the Cortex‑M core, not the STM32 peripheral set.

Core exceptions have fixed, architecturally higher priority than any NVIC‑managed interrupt.

This is why:

  • You never call NVIC_EnableIRQ(SysTick_IRQn)

  • You never set SysTick priority

  • It always preempts peripheral ISRs

5️⃣ Summary: What Happens If SysTick and TIM6 Interrupt at the Same Time?

  1. Both events occur on the same cycle
  2. SysTick is a core exception → higher priority
  3. CPU enters SysTick_Handler first
  4. TIM6 interrupt becomes pending
  5. When SysTick_Handler finishes, NVIC dispatches TIM6 ISR
  6. TIM6 ISR runs normally

diagram:

flowchart TD
    A[SysTick event] -->|Higher priority| C[SysTick_Handler]
    B[TIM6 update event] -->|Lower priority| D[TIM6 pending]
    C --> E[Return from SysTick]
    E -->|Tail-chaining| F[TIM6 ISR runs]

📌 Challenge Activity: Visualizing Priority

Students:

  • Configure SysTick at 1 kHz
  • Configure TIM6 at 1 kHz
  • Toggle different pins in each ISR
  • Observe on the oscilloscope

Expected Results:

  • SysTick edges always appear first
  • TIM6 edges follow immediately after
  • No jitter except ISR execution time

This makes priority visible.

6️⃣ Advanced NVIC Functions